As the speed and complexity of processors and other integrated circuit components has increased, the need for high-speed input/output (IO) has also increased. Conventional packaging technologies are running into physical limitation making them unable to meet all the requirements. New technologies, such as optical IO integrated on a die, are becoming a reality. Current manufacturing processes and designs have limited ability to adapt to these new technologies. Additionally, current conventional processing of integrated circuits uses the same substrate design structure for power delivery and for signal IO. Neither one of these can be optimized, either for performance versus cost or other factors, as some of the requirements of one area restricts the optimization of the other.
In addition, due to the increasing trends of higher current and high I/O count, using the same design structure drives a substantial increase in pin count, hence an increase in body size and package cost. Separating power and signal delivery paths may improve signal integrity due to less discontinuity, better impedance matching and reduction latency. At the same time, more pins can be dedicated for power delivery.